Fin field effect transistors (finFETs) are leading candidates to enable the scaling of gate lengths to 25 nm and below. When using finFETs, it is desirable to lower the gate resistance to improve performance characteristics such as the effective AC resistance (AC Reff) and the maximum operating frequency (RF fmax). One approach to lowering the gate resistance is polysilicon pre-doping. Pre-doping the polysilicon with boron or arsenic and then performing a rapid thermal anneal (RTA) is commonly used in fabricating planar CMOS devices. However, with the 3D structure of a fin FET, it is difficult to achieve a uniform high doping concentration down to the line in-between the fins through such a conventional implant and thermal diffusion. Additionally, this requires an extra mask step to form both nFET and pFET devices formed.
Another approach to lowering the gate resistance is increasing the thickness of the gate silicide. The thickness of the gate silicide can be increased by increasing the initial nickel platinum (NiPt) deposition thickness or by performing RTA at a higher temperature. However, both of these methods for increasing the thickness of the gate silicide also increase the thickness of the silicide in the source/drain regions. This leads to silicide encroachment and increased junction leakage.